Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldc.d CP#, CRd, Rp[disp]

CP#(CRd+1:CRd) = *(Rp + (ZE(disp8) << 2));
# ∈ {0, 1, …, 7}

Rev1+

111010011010

Rp

CP #

1

CRd[3:1]

0

disp8

12

4

3

1

3

1

8

2

ldc.d CP#, CRd, --Rp

Rp = Rp-8;
CP#(CRd+1:CRd) = *(Rp);
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

0

CRd[3:1]

001010000

12

4

3

1

3

9

3

ldc.d CP#, CRd, Rb[Ri<<sa]

CP#(CRd+1:CRd) = *(Rb + (Ri << sa2));
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

1

CRd[3:1]

001

sa2

Ri

12

4

3

1

3

3

2

4

4

ldc.w CP#, CRd, Rp[disp]

CP#(CRd) = *(Rp + (ZE(disp8) << 2));
# ∈ {0, 1, …, 7}

Rev1+

111010011010

Rp

CP #

0

CRd

k8

12

4

3

1

4

8

5

ldc.w CP#, CRd, --Rp

Rp = Rp-4;
CP#(CRd) = *(Rp);
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

0

CRd

01000000

12

4

3

1

4

8

6

ldc.w CP#, CRd, Rb[Ri<<sa]

CP#(CRd) = *(Rb + (Ri << sa2));
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

1

CRd

00

sa2

Ri

12

4

3

1

4

2

2

4

Description

Reads the memory location specified into the addressed coprocessor.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Example:

ldc.d
CP2, CR0, R2[0]